2008年3月18日 星期二

PCI LA analysis - 080321

Address Phase

  • PCICLK=rising edge
  • CBE=X
  • AD[31:16]=XXXX
  • AD[15:0]=XXXX
  • FRAMEN=Low
Data Phase
  • PCICLK=rising edge
  • IRDY=Low
  • TRDY=Low
  • AD[31:16]=XXXX
  • AD[15:0]=XXXX
LA sample的訊號有時會看到CLK的rising edge在訊號轉變的中間,要怎麼決定它的值呢?
因為PCI有定義setup/hold time,所以舊的值(應該)至少要在CLK的sample event前維持Tsu,在CLK的sample event後維持Th這段時間
PCI bus spec v2.2 Tsu=min 7ns, Th=min 0ns


Setup and Hold Times for Latches
  • Setup Time (Tsu) is the minimum time interval for which the input signal must be stable (unchanging) prior to the sampling event of the clock for the input signal to be recognized correctly.
  • Hold Time (Th) is the minimum time interval for which the input signal must be stable (unchanging) following the sampling event of the clock for the input signal to be recognized correctly.



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