PCI Memory/IO access

Memory read/write is DWORD aligned, and can burst.
I/O read/write is byte aligned, and can only do byte, word, DWORD operation

PCI Local Bus Specification

Chapter 3 Bus Operation

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C/BE[3::0]# Command Type
0000 Interrupt Acknowledge
0001 Special Cycle
0010 I/O Read
0011 I/O Write
0100 Reserved
0101 Reserved
0110 Memory Read
0111 Memory Write
1000 Reserved
1001 Reserved
1010 Configuration Read
1011 Configuration Write
1100 Memory Read Multiple
1101 Dual Address Cycle
1110 Memory Read Line
1111 Memory Write and Invalidate

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3.2.2. Addressing

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When a transaction is initiated on the interface, each potential target compares the address with its Base Address register(s) to determine if it is the target of the current transaction. if it is the target, the device asserts DEVSEL# to claim the access.

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3.2.2.1 I/O Space Decoding
In the I/O Address Space, all 32 AD lines are used to provide a full byte address.

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3.2.2.2 Memory Space Decoding
In the Memory Address Space, the AD[31:02] bus provides a DWORD aligned address. AD[1::0] are not part of the address decode.