PCIe Messages sent by Root Complex

PCIe Messages sent by Root Complex is by RC itself or by software?

per PCIe base spec rev2.0
RC would send those messages

• PM_Active_State_Nak
  used by upstream port to reject to enter L1 state, should be sent by RC automatically.
  p322
  

  Rules in case of rejection:
  

  • In the case of a rejection, the Upstream component must schedule, as soon as possible, a rejection by sending the PM_Active_State_Nak Message to the Downstream component. Once the PM_Active_State_Nak Message is sent, the Upstream component is permitted to initiate any TLP or DLLP transfers.

  
  
• PME_Turn_Off
  seems could be sent (cause?) by software
  p297
  

  The following example sequence illustrates the multi-step Link state transition process leading up to entering a system sleep state:
  

  1. System software directs all Functions of a Downstream component to D3hot.
  2. The Downstream component then initiates the transition of the Link to L1 as required.
  3. System software then causes the Root Complex to broadcast the PME_Turn_Off Message in preparation for removing the main power source.
  4. This Message causes the subject Link to transition back to L0 in order to send it and to enable the Downstream component to respond with PME_TO_Ack.
  5. After sending the PME_TO_Ack, the Downstream component initiates the L2/L3 Ready transition protocol.

  L0 → L1 → L0 → L2/L3 Ready

  
  
• Unlock
  seems RC should send it automatically
  p376
  

  6.5. Locked Transactions
  
  6.5.1. Introduction
  
  Locked Transaction support is required to prevent deadlock in systems that use legacy software which causes the accesses to I/O devices. Note that some CPUs may generate locked accesses as a result of executing instructions that implicitly trigger lock. Some legacy software misuses these transactions and generates locked sequences even when exclusive access is not required.
  
  (........................)
  
  6.5.2. Initiation and Propagation of Locked Transactions - Rules
  
  Locked transaction sequences are generated by the Host CPU(s) as one or more reads followed by a number of writes to the same location(s). When a lock is established, all other traffic is blocked from using the path between the Root Complex and the locked Legacy Endpoint or Bridge.
  

  • A locked transaction sequence or attempted locked transaction sequence is initiated on PCI Express using the “lock”–type Read Request/Completion (MRdLk/CplDLk) and terminated with the Unlock Message

  
  

• Set_Slot_Power_Limit
  seems RC should send it automatically
  p77
  

  2.2.8.5. Slot Power Limit Support
  
  (........................)
  
  The Set_Slot_Power_Limit Message includes a one DW data payload. The data payload is copied from the Slot Capabilities register of the Downstream Port and is written into the Device Capabilities register of the Upstream Port on the other side of the Link. Bits 1:0 of Byte 1 of the data payload map to the Slot Power Limit Scale field and bits 7:0 of Byte 0 map to the Slot Power Limit Value field. Bits 7:0 of Byte 3, 7:0 of Byte 2, and 7:2 of Byte 1 of the data payload must be set to all 0’s by the Transmitter and ignored by the Receiver. This Message must be sent automatically by the Downstream Port (of a Root Complex or a Switch) when one of the following events occurs:
  

  • On a Configuration Write to the Slot Capabilities register (see Section 7.8.9) when the Data Link Layer reports DL_Up status.
  • Any time when a Link transitions from a non-DL_Up status to a DL_Up status(see Section 2.9.2). This Transmission is optional if the Slot Capabilities register has not yet been initialized.

  The component on the other side of the Link (with Endpoint, Switch, or Bridge Functions) that receives Set_Slot_Power_Limit Message must copy the values in the data payload into the Device Capabilities register associated with the component’s Upstream Port. PCI Express components that are targeted exclusively for integration on the system planar (e.g., system board) as well as components that are targeted for integration on a card/module where power consumption of the entire card/module is below the lowest power limit specified for the card/module form factor (as defined in the corresponding form factor specification) are permitted to hardwire the value 0b in the Slot Power Limit Scale and Slot Power Limit Value fields of the Device Capabilities register, and are not required to copy the Set_Slot_Power limit payload into that register.

• Vendor-defined messages
  "Not defined" means RC could never send it automatically!!!
  p77
  

  2.2.8.6. Vendor_Defined Messages
  
  The Vendor_Defined Messages allow expansion of PCI Express messaging capabilities, either as a general extension to the PCI Express Specification or a vendor-specific extension. Such extensions are not covered specifically in this document, although future revisions of this specification may use this mechanism to define new Messages (see below). This section defines the rules associated with these Messages generically.
  
  (...........................)
  
  

  • A data payload may be included with either type of Vendor_Defined Message (TLP type is Msg if no data payload is included and MsgD if a data payload is included)