Definition of Endianness
- Byte ordering to represent some kind of data
- Particular attribute of a representation format
- Is about how to interpret data
- Usually when there are communication, or sharing information
- Between computers in a network
- Or between components in a SoC, e.g. cpu, memory, devices
- Endianness of both sides have to be the same to communicate correctly
- Or swap data by some hardware/software mechanism
- To share information between hosts of different endianness typically uses one of two strategies
- Single endianness for sharing data
- Most Internet standards specify big-endian
- Allow hosts to share data in any endianness and mark which one they are using
- Single endianness for sharing data
- NUXI problem (aka. endian problem)
- Problem of transferring data between computers with differing byte order
- File format
- binary file created on a computer is read on another computer with different endian
- Usually when there are communication, or sharing information
- Big-endian
- High-order byte of the number is stored in memory at the lowest address
- Low-order byte of the number is stored in memory at the highest address
- Motorola 68000, SPARC and System/370
- Little-endian
- Low-order byte of the number is stored in memory at the lowest address
- High-order byte of the number is stored in memory at the highest address
- X86, MOS Technology 6502, DEC VAX
- Bi-endian (aka. bytesexual)
- Architectures that can be configured either way
- ARM, PowerPC (but not the PPC970/G5), DEC Alpha, MIPS, PA-RISC and IA64
- Middle-endian (aka. mixed-endian)
- PDP-11
Endianness in SoC
Components in SoC
- CPU
- Would require memory in a specific endianness
- Changing endianness in a SoC usually means changing the endianness of CPU.
- Memory
- (?)Memory is actually a passive device, i.e. it just give the data that was written, no matter the endianness
(?)
(Absolutely wrong. the endianness would cause different word/byte behavior...)
memory have it's endianness, but would fulfill the expectation of CPU - Sometime memory controller may access memory in one endianness, and access bus in another endianness (to fit the expectation of CPU)
- e.g. data stored in memory is Little Endian, but memory controller would always swap the data to behave as Big Endian memory.
- e.g. data stored in memory is Little Endian, but memory controller would always swap the data to behave as Big Endian memory.
- (?)Memory is actually a passive device, i.e. it just give the data that was written, no matter the endianness
- Device
- change endianness as CPU do
- keep the same endianness
- use hardware wrapper to swap the data
- use software to swap the data
Endianness of ARM CPU
- Little Endian
- Big Endian (a.k.a. word-invariant big endian, BE-32)
- for ARMv4/v5 CPU
- word-invariant: word access doesn't require swapping
- BE8 (a.k.a. byte-invariant big endian)
- for ARMv6 CPU
- byte-invariant: byte access doesn't require swapping
RealView Compilation Tools for µVision Linker Reference Guide Version 4.0 Linker Command-line Options
- --be32
- This option specifies legacy Word Invariant Addressing big-endian mode, that is, identical to big-endian images prior to ARMv6.
- Produces big-endian code and data.
- Word Invariant Addressing mode is the default mode for all pre-ARMv6 big-endian images.
- --be8
- This option specifies ARMv6 Byte Invariant Addressing big-endian mode.
- This is the default Byte Addressing mode for ARMv6 big-endian images
- for input objects that have been compiled/assembled as big-endian, linker reverses the endianness of the instructions to give
- little-endian code (instruction)
- big-endian data
- little-endian code (instruction)
- Byte Invariant Addressing mode is only available on ARM processors that support ARMv6 and above.
How to define endianness of CPU?
by the data input to and output from CPU, e.g.
(data in 0xD31->D0 order)
Little endian: 0x12345678+0xeeddccbb=0x0112_2333
Big endian : 0x12345678+0xeeddccbb=0x0012_2334
How to define endianness of memory?
??
I think memory should just return data in it's ordering. it's the responsibility of the "user" (e.g. CPU, Device) to decide the endianness first, and then to interpret the data in memory. So if the CPU is in big endian mode, implies the data in memory is big endian too, and vice versa.
but it seems that many memory do require endianness setting, why is that?
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0269a/Babjaiga.html?resultof=%22%65%6e%64%69%61%6e%22%20
http://infocenter.arm.com/help/topic/com.arm.doc.ddi0269a/Cegbbbab.html?resultof=%22%65%6e%64%69%61%6e%22%20
??
Facts of ARM11MPCore BE8 Mode
- compiled binary(with --be8) have Little Endian instruction, Big Endian data
- loading instructions would NOT cause a swap
- loading data would cause a swap
- thus, in CPU, it is Little Endian instruction and data
- 0x12345678 (in source code) -(compiled & loaded to memory)-> 0x78563412 (in RAM) -(loaded to CPU register)-> 0x12345678 (in CPU register)
- the operation seems like Little endian operation, e.g. 0x12345678+0xeeddccbb=0x01122333
[wiki] 位元組序
http://zh.wikipedia.org/w/index.php?title=%E5%AD%97%E8%8A%82%E5%BA%8F&variant=zh-tw
Endianness
http://en.wikipedia.org/wiki/Endianness
NUXI problem
http://catb.org/jargon/html/N/NUXI-problem.html
swab
http://catb.org/jargon/html/S/swab.html
RealView Linker Reference Guide: --be8
http://www.keil.com/support/man/docs/armlinkref/armlinkref_chdheicg.htm
RealView Linker Reference Guide: --be32
http://www.keil.com/support/man/docs/armlinkref/armlinkref_chddbdgb.htm
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