Linux barriers and ARM barriers

./Documentation/memory-barriers.txt

SMP barriers semantics
http://eeek.borgchat.net/lists/linux-arch/msg09402.html
http://marc.info/?l=linux-arch&m=126752718913718&w=2
http://www.spinics.net/lists/linux-arch/msg09402.html
http://article.gmane.org/gmane.linux.kernel.cross-arch/5250

http://www.spinics.net/lists/linux-arch/msg09406.html

The SMP barriers are only required to order cacheable accesses. The plain (non-SMP) barriers (mb, wmb, rmb) are required to order both cacheable and non-cacheable accesses.

ARM11 MPCore™ Processor r2p0 Technical Reference Manual

Data Synchronization Barrier
The Data Synchronization Barrier (DSB) operation acts as a special kind of memory barrier. In the program flow, the DSB occurs at the MCR instruction that performs the DSB. The DSB completes when:

• all explicit reads and writes before the DSB complete
• all Cache, Branch predictor and TLB maintenance operations before the DSB complete.

No instruction after the DSB can execute until the DSB completes.

Data Memory Barrier
The Data Memory Barrier (DMB) is a general memory barrier with the following behavior. This description considers the program flow as executing instructions in program order. The DMB occurs at the MCR instruction that performs the DMB.

• Any explicit memory access by an instruction before the DMB is globally observed before any memory accesses caused by an instruction after the DMB.
• The DMB has no effect on the ordering of any other instructions executing on the processor.

As such, DMB ensures the apparent order of the explicit memory operations before and after the DMB instruction, but does not ensure the completion of those memory operations. For more information see the ARM Architecture Reference Manual.

ARM: Change the mandatory barriers implementation
http://www.spinics.net/lists/arm-kernel/msg84605.html

The mandatory barriers (mb, rmb, wmb) are used even on uniprocessor
systems for things like ordering Normal Non-cacheable memory accesses
with DMA transfer (via Device memory writes). The current implementation
uses dmb() for mb() and friends but this is not sufficient. The DMB only
ensures the relative ordering of the observability of accesses by other
processors or devices acting as masters. In case of DMA transfers
started by writes to device memory, the relative ordering is not ensured
because accesses to slave ports of a device are not considered
observable by the DMB definition.

A DSB is required for the data to reach the main memory (even if mapped
as Normal Non-cacheable) before the device receives the notification to
begin the transfer. Furthermore, some L2 cache controllers (like L2x0 or
PL310) buffer stores to Normal Non-cacheable memory and this would need
to be drained with the outer_sync() function call.

The patch also allows platforms to define their own mandatory barriers
implementation by selecting CONFIG_ARCH_HAS_BARRIERS and providing a
mach/barriers.h file.

Note that the SMP barriers are unchanged (being DMBs as before) since
they are only guaranteed to work with Normal Cacheable memory.