2010年2月25日 星期四

人因魔力影音霸 DB-204

DB204 韌體更新
http://www.ergotech.com.tw/c_main2007/download-new.htm


過年的時候帶著 兆赫藍光奇機 回家,還特地買了HDMI線,結果發現忘了帶 遙控器.....
無言................

只好再跑一趟順發,發現這台規格都不錯,重點是,有SD,內建硬碟,再看到COPY,就衝了

優點(相對 兆赫藍光奇機)
  1. 有SD卡
  2. 可內建3.5吋SATA II硬碟
  3. 面板上有按鍵,可做些基本操作,如copy、播放
缺點
  1. 不能錄影
  2. 硬碟只支援到1TB
  3. 機殼邊緣有點銳利
  4. SD卡槽沒標方向
  5. 遙控器太複雜;英文介面;
  6. 機殼螺絲很複雜

不過 人因魔力影音霸 與 兆赫藍光奇機 的介面一整個像,應該是都是從同一個IC廠出來的solution改來的吧








光光要拆個機殼,背板上有3種,共7顆螺絲;還有,那個QC Warranty是怎麼回事? 裝個硬碟就沒保固?








良興Eclife購物網站 - 人因 魔力影音霸播放器 DB204
http://www.eclife.com.tw/tv_mp3/moreinfo_34569.htm

國產高清機DB204,幾乎通吃所有影音格式,並可數位輸� X24/192的WAV檔
http://www.myav.com.tw/bbs/showthread.php?s=adb2706d516e3ec5b5629833f92de077&threadid=413435

Mobile01 - 人因魔力影音霸DB204開箱文及使用心得
http://www.mobile01.com/topicdetail.php?f=347&t=1387956&r=2&last=17163037#

人因科技 魔力影音霸 DB206 規格出現了..
http://www.play01.com/topicdetail.php?f=347&t=1419960&m=f&p=1&img=0#

請問人因DB206與DB204的差別?
http://www.mobile01.com/topicdetail.php?f=347&t=1414192&p=1

瑞昱RTD1073媒體處理器支援所有HD格式
http://www.eettaiwan.com/ART_8800583807_876045_NP_f573ed48.HTM

2010年2月24日 星期三

How to move a big branches to a new base?

http://marc.info/?l=git&m=126715471207185&w=2

I have a branch that have about 10 descendent branches. Now I would like to move this branch, and all the descendent branches, to a new base, and I might need to do so quiet frequently.

My "dirty" way is to rebase step by step, it takes about 15-20 rebases, but the branches is somehow complicated, and this seems error-prone to me.

Is there a clean way to do so?

git: squash my commit?
http://stackoverflow.com/questions/204461/git-squash-my-commit

squashing commits with rebase
http://www.gitready.com/advanced/2009/02/10/squashing-commits-with-rebase.html

git awsome-ness [git rebase --interactive]
http://blog.madism.org/index.php/2007/09/09/138-git-awsome-ness-git-rebase-interactive


A successful Git branching model
http://nvie.com/git-model

git pull (w/ --ff) : fetch and merge with fast forwarding
git pull --no-ff : fetch and merge without fast forwarding
git pull --rebase : fetch and rebase

merge/rebase

Use merge instead for temporary tests: merge master to the target branch.

2010年2月23日 星期二

OpenVPN

Kernel config

Device Drivers --->
[*] Network device support --->
<M> Universal TUN/TAP device driver support


Ethernet Bridging
http://openvpn.net/index.php/open-source/documentation/miscellaneous/76-ethernet-bridging.html


  1. Start from server.conf or client.conf /usr/share/doc/openvpn/examples/sample-config-files/, and copy the script bridge-star and bridge-stop from http://openvpn.net/index.php/open-source/documentation/miscellaneous/76-ethernet-bridging.html#linuxscript
    server.conf and bridge-start
    diff --git a/bridge-start b/bridge-start
    index bfbbdc5..b77510a 100755
    --- a/bridge-start
    +++ b/bridge-start
    @@ -15,9 +15,9 @@ tap="tap0"
    # Define physical ethernet interface to be bridged
    # with TAP interface(s) above.
    eth="eth0"
    -eth_ip="192.168.8.4"
    -eth_netmask="255.255.255.0"
    -eth_broadcast="192.168.8.255"
    +eth_ip="10.1.1.23"
    +eth_netmask="255.0.0.0"
    +eth_broadcast="10.255.255.255"

    for t in $tap; do
    openvpn --mktun --dev $t
    diff --git a/server.conf b/server.conf
    index a439520..6aa3cb2 100644
    --- a/server.conf
    +++ b/server.conf
    @@ -49,8 +49,8 @@ proto udp
    # On most systems, the VPN will not function
    # unless you partially or fully disable
    # the firewall for the TUN/TAP interface.
    -;dev tap
    -dev tun
    +dev tap0
    +;dev tun

    # Windows needs the TAP-Win32 adapter name
    # from the Network Connections panel if you
    @@ -93,7 +93,7 @@ dh dh1024.pem
    # Each client will be able to reach the server
    # on 10.8.0.1. Comment this line out if you are
    # ethernet bridging. See the man page for more info.
    -server 10.8.0.0 255.255.255.0
    +;server 10.8.0.0 255.255.255.0

    # Maintain a record of client <-> virtual IP address
    # associations in this file. If OpenVPN goes down or
    @@ -112,7 +112,7 @@ ifconfig-pool-persist ipp.txt
    # (start=10.8.0.50 end=10.8.0.100) to allocate
    # to connecting clients. Leave this line commented
    # out unless you are ethernet bridging.
    -;server-bridge 10.8.0.4 255.255.255.0 10.8.0.50 10.8.0.100
    +server-bridge 10.1.1.23 255.0.0.0 10.1.101.100 10.1.101.200

    # Configure server mode for ethernet bridging
    # using a DHCP-proxy, where clients talk

    client.conf
    diff --git a/rootfs/root/client.conf b/rootfs/root/client.conf
    index a5f5074..ee47af9 100644
    --- a/rootfs/root/client.conf
    +++ b/rootfs/root/client.conf
    @@ -20,8 +20,8 @@ client
    # On most systems, the VPN will not function
    # unless you partially or fully disable
    # the firewall for the TUN/TAP interface.
    -;dev tap
    -dev tun
    +dev tap
    +;dev tun

    # Windows needs the TAP-Win32 adapter name
    # from the Network Connections panel
    @@ -39,7 +39,7 @@ proto udp
    # The hostname/IP and port of the server.
    # You can have multiple remote entries
    # to load balance between the servers.
    -remote my-server-1 1194
    +remote 172.20.20.1 1194
    ;remote my-server-2 1194

    # Choose a random host from the remote
  2. Generate certificate and keys
    cd /usr/share/doc/openvpn/examples/easy-rsa/2.0
    source ./vars #info in var could be changed if needed
    ./clean-all # rm ./key/
    ./build-ca # generate CA certificate ./key/ca.*
    ./build-key-server server # generate server key
    ./build-dh #generate Diffie Hellman parameters
    openvpn --genkey --secret keys/ta.key # generate tls-auth key
    ./build-key client # generate client key
  3. goto /usr/share/doc/openvpn/examples/easy-rsa/2.0/key, and run
    Start Server:
    bridge-start; openvpn path/to/your/server.conf

    Stop Server:
    killall openvpn; bridge-stop;

    Start Client
    openvpn path/to/your/client.conf


Server Side
Fri Feb 26 17:44:25 2010 OpenVPN 2.1_rc19 i486-pc-linux-gnu [SSL] [LZO2] [EPOLL] [PKCS11] built on Oct 13 2009
Fri Feb 26 17:44:25 2010 NOTE: when bridging your LAN adapter with the TAP adapter, note that the new bridge adapter will often take on its own IP address that is different from what the LAN adapter was previously set to
Fri Feb 26 17:44:25 2010 NOTE: OpenVPN 2.1 requires '--script-security 2' or higher to call user-defined scripts or executables
Fri Feb 26 17:44:25 2010 Diffie-Hellman initialized with 1024 bit key
Fri Feb 26 17:44:25 2010 /usr/bin/openssl-vulnkey -q -b 1024 -m <modulus omitted>
Fri Feb 26 17:44:25 2010 TLS-Auth MTU parms [ L:1574 D:138 EF:38 EB:0 ET:0 EL:0 ]
Fri Feb 26 17:44:25 2010 TUN/TAP device tap0 opened
Fri Feb 26 17:44:25 2010 TUN/TAP TX queue length set to 100
Fri Feb 26 17:44:25 2010 Data Channel MTU parms [ L:1574 D:1450 EF:42 EB:135 ET:32 EL:0 AF:3/1 ]
Fri Feb 26 17:44:25 2010 Socket Buffers: R=[114688->131072] S=[114688->131072]
Fri Feb 26 17:44:25 2010 UDPv4 link local (bound): [undef]:1194
Fri Feb 26 17:44:25 2010 UDPv4 link remote: [undef]
Fri Feb 26 17:44:25 2010 MULTI: multi_init called, r=256 v=256
Fri Feb 26 17:44:25 2010 IFCONFIG POOL: base=10.8.0.50 size=51
Fri Feb 26 17:44:25 2010 IFCONFIG POOL LIST
Fri Feb 26 17:44:25 2010 Initialization Sequence Completed



Client Side
Fri Feb 26 20:46:55 2010 OpenVPN 2.1_rc18 arm-unknown-linux-gnu [SSL] [LZO2] [EPOLL] built on Feb 26 2010
Fri Feb 26 20:46:55 2010 NOTE: OpenVPN 2.1 requires '--script-security 2' or higher to call user-defined scripts or executables
Fri Feb 26 20:46:55 2010 LZO compression initialized
Fri Feb 26 20:46:55 2010 Control Channel MTU parms [ L:1574 D:138 EF:38 EB:0 ET:0 EL:0 ]
Fri Feb 26 20:46:55 2010 Data Channel MTU parms [ L:1574 D:1450 EF:42 EB:135 ET:32 EL:0 AF:3/1 ]
Fri Feb 26 20:46:55 2010 Local Options hash (VER=V4): 'd79ca330'
Fri Feb 26 20:46:55 2010 Expected Remote Options hash (VER=V4): 'f7df56b8'
Fri Feb 26 20:46:55 2010 Socket Buffers: R=[112640->131072] S=[112640->131072]
Fri Feb 26 20:46:55 2010 UDPv4 link local: [undef]
Fri Feb 26 20:46:55 2010 UDPv4 link remote: 172.20.20.1:1194
Fri Feb 26 20:46:55 2010 TLS: Initial packet from 172.20.20.1:1194, sid=ac8f4fc8 695625be
Fri Feb 26 20:46:55 2010 VERIFY OK: depth=1, /C=US/ST=CA/L=SanFrancisco/O=Fort-Funston/CN=Fort-Funston_CA/emailAddress=me@myhost.mydomain
Fri Feb 26 20:46:55 2010 VERIFY OK: nsCertType=SERVER
Fri Feb 26 20:46:55 2010 VERIFY OK: depth=0, /C=US/ST=CA/L=SanFrancisco/O=Fort-Funston/CN=server/emailAddress=me@myhost.mydomain
Fri Feb 26 20:46:55 2010 Data Channel Encrypt: Cipher 'BF-CBC' initialized with 128 bit key
Fri Feb 26 20:46:55 2010 Data Channel Encrypt: Using 160 bit message hash 'SHA1' for HMAC authentication
Fri Feb 26 20:46:55 2010 Data Channel Decrypt: Cipher 'BF-CBC' initialized with 128 bit key
Fri Feb 26 20:46:55 2010 Data Channel Decrypt: Using 160 bit message hash 'SHA1' for HMAC authentication
Fri Feb 26 20:46:55 2010 Control Channel: TLSv1, cipher TLSv1/SSLv3 DHE-RSA-AES256-SHA, 1024 bit RSA
Fri Feb 26 20:46:55 2010 [server] Peer Connection Initiated with 172.20.20.1:1194
Fri Feb 26 20:46:57 2010 SENT CONTROL [server]: 'PUSH_REQUEST' (status=1)
Fri Feb 26 20:46:57 2010 PUSH: Received control message: 'PUSH_REPLY,route-gateway 10.1.1.23,ping 10,ping-restart 120,ifconfig 10.1.101.100 255.0.0.0'
Fri Feb 26 20:46:57 2010 OPTIONS IMPORT: timers and/or timeouts modified
Fri Feb 26 20:46:57 2010 OPTIONS IMPORT: --ifconfig/up options modified
Fri Feb 26 20:46:57 2010 OPTIONS IMPORT: route-related options modified
Fri Feb 26 20:46:57 2010 TUN/TAP device tap0 opened
Fri Feb 26 20:46:57 2010 TUN/TAP TX queue length set to 100



Client connect failed with

Wed Dec 31 17:15:16 1969 NOTE: OpenVPN 2.1 requires '--script-security 2' or higher to call user-defined scripts or executables
Wed Dec 31 17:15:16 1969 Re-using SSL/TLS context
Wed Dec 31 17:15:16 1969 Control Channel MTU parms [ L:1573 D:138 EF:38 EB:0 ET:0 EL:0 ]
Wed Dec 31 17:15:16 1969 Data Channel MTU parms [ L:1573 D:1450 EF:41 EB:4 ET:32 EL:0 ]
Wed Dec 31 17:15:16 1969 Local Options hash (VER=V4): '2c50bd2c'
Wed Dec 31 17:15:16 1969 Expected Remote Options hash (VER=V4): '0ddbb6e3'
Wed Dec 31 17:15:16 1969 Socket Buffers: R=[112640->131072] S=[112640->131072]
Wed Dec 31 17:15:16 1969 UDPv4 link local: [undef]
Wed Dec 31 17:15:16 1969 UDPv4 link remote: 172.20.20.1:1194
Wed Dec 31 17:15:16 1969 TLS: Initial packet from 172.20.20.1:1194, sid=ca5eb197 b60ea9fa
Wed Dec 31 17:15:16 1969 VERIFY ERROR: depth=1, error=certificate is not yet valid: /C=US/ST=CA/L=SanFrancisco/O=Fort-Funston/CN=Fort-Funston_CA/emailAddress=me@myhost.mydomain
Wed Dec 31 17:15:16 1969 TLS_ERROR: BIO read tls_read_plaintext error: error:14090086:SSL routines:SSL3_GET_SERVER_CERTIFICATE:certificate verify failed
Wed Dec 31 17:15:16 1969 TLS Error: TLS object -> incoming plaintext read error
Wed Dec 31 17:15:16 1969 TLS Error: TLS handshake failed
Wed Dec 31 17:15:16 1969 TCP/UDP: Closing socket
Wed Dec 31 17:15:16 1969 SIGUSR1[soft,tls-error] received, process restarting
Wed Dec 31 17:15:16 1969 Restart pause, 2 second(s)

Re: [Openvpn-users] Help with OpenVPN & DD-WRT
http://openvpn.net/archive/openvpn-users/2006-08/msg00091.html
- check the current time on the DD-WRT
- use openssl to check the contents of the certificate
openssl -in certfile.pem -noout -text
In my case, it is the time of my device is not set properly.


Community Software Overview
http://openvpn.net/index.php/open-source.html

OpenVPN - Downloads
http://openvpn.net/index.php/open-source/downloads.html

HOWTO
http://openvpn.net/index.php/open-source/documentation/howto.html

Determining whether to use a routed or bridged VPN
http://openvpn.net/index.php/open-source/documentation/howto.html#vpntype

OpenVPN 建置方案
http://www.study-area.org/tips/openvpn.html

[wiki] OpenVPN
http://en.wikipedia.org/wiki/OpenVPN

使用 OpenVPN 建置 VPN
http://www.cdchen.idv.tw/node/963

使用 OpenVPN
http://macblog2.blogspot.com/2005/06/openvpn.html

OpenVPN GUI for Windows
http://openvpn.se/

2010年2月20日 星期六

prelink

Dynamic linking in the kernel
http://www.spinics.net/lists/kernel/msg1000682.html
http://www.spinics.net/lists/kernel/msg1000692.html

Actually, the more expensive part of shared libraries are the page
faults from filling in the relocations and we already have a mechanism
to save that cost, it's called 'prelink'.


[wiki] prelink
http://en.wikipedia.org/wiki/Prelink

Gentoo Linux Prelink 指南
http://www.gentoo.org/doc/zh_tw/prelink-howto.xml

[Jing's House] linux prelink
http://jingshouse.blogspot.com/2007/07/linux-prelink.html

2010年2月17日 星期三

製作燈籠

彩繪燈籠製作方法 --> 專業的傳統燈籠製作
http://year.ibook.idv.tw/lantern.php

小呀米燈籠製作教學 - 小蘿蔔 用電線鐵絲
http://www.mingtong.com.tw/art/yamie/index.htm

燈籠製作 - 摺紙 燈籠
http://www.chinalane.org/life009/101studio/00000796.html

環保燈籠製作 - 阿Q桶麵的包裝紙盒、壁報紙、廣告紙、流蘇、燈籠提把、剪紙圖案
http://tw.myblog.yahoo.com/small-green/article?mid=75&prev=117&l=f&fid=12

【燈籠DIY】環保燈籠在家做‧炫酷「森林狩獵」手工燈籠
1. 回收空奶粉罐
2. 回收紙盒 (或紙板一張)
http://fun.kimy.com.tw/PostDetail.aspx?PostID=3402

利用環保材料製作花燈 培養學生環保概念及藝術技巧 --> 一堆環保燈籠
http://dns.kces.tyc.edu.tw/~dida/academic/files/980218.htm

環保創意燈籠製作 --> 一堆環保燈籠
http://163.30.170.130/forverschool/read.php?26

燈籠製作 ----> (買一個白的用畫的)
http://fcu.org.tw/~ju/teacher/95aActive/denglong/denglong.html

2010年2月16日 星期二

ARM cache coherency issue (with speculatively prefetch)

Re: USB mass storage and ARM cache coherency
http://lkml.org/lkml/2010/2/16/80

On map, buffers are cleaned if they're being used for DMA_TO_DEVICE and DMA_BIDIRECTIONAL, or invalidated in the case of DMA_FROM_DEVICE.

(On unmap, nothing else is done)

However, because ARM CPUs (ARMv7, or some of that higher than ARM11 MPCore) can now speculatively prefetch, just leaving it at that (do nothing on unmap) results in corruption of buffers used for DMA. So we have to invalidate DMA_FROM_DEVICE and DMA_BIDIRECTIONAL buffers on unmap to ensure coherency with DMA operations.

If the CPU writes to a DMA_FROM_DEVICE buffer between map and unmap, the writes can sit in the cache, and on unmap, they will be discarded.

(Mixing PIO and DMA buffers wasn't a big issue with previous ARM CPUs, whoes unmap didn't do cache operation; while with ARM CPUs with speculatively perfetch, invalidating on unmap would invalidate the valid data that cached by PIO.)

Cleaning the cache on unmap is not an option; that too can lead to DMA buffer corruption in the DMA case.

USB and associated host driver must abide by the DMA API buffer ownership rules otherwise the result will be data corruption; either that or USB/host driver people need to have a discussion with the DMA API authors to remove this sensible "restriction".

2010年2月9日 星期二

PIO device with cache coherency

USB mass storage and ARM cache coherency
http://lkml.org/lkml/2010/1/29/151


(1st issue: I/D cache coherency)

I've been trying for some time to use a rootfs (ext2) on a USB memory
stick on ARM platforms but without any success. The USB HCD driver is
ISP1760 which doesn't use DMA.

ARM has a Harvard cache architecture and what I get is incoherency
between the I and D caches
. The CPU I'm using (ARM11MPCore) has PIPT
caches with D-cache lines allocation on write.

Basically, when user space tries to execute from a new page, it faults
and the data is requested via the VFS layer, SCSI block device and USB
mass storage from the ISP1760 driver. The page is then mapped into user
space and update_mmu_cache() called.

However, since the driver is PIO, the data copied from the USB device
into RAM gets stuck in the D-cache. On the above page requesting path
there is no call to flush_dcache_page() to handle D-cache maintenance
(for DMA drivers, that's handled by the DMA API).

Since the USB mass storage code has the information about the USB driver
capabilities (DMA or PIO), it looks like the best place to call
flush_dcache_page(). But I got lost in the SCSI emulation and all my
attempts failed to get a working rootfs.

Adding flush_dcache_page() higher up in mpage_end_io_read() solves the
problem but that's not the correct fix as it has wider implications and
it's not needed for DMA-capable devices.

(.................)

isp1760: Flush the D-cache for the pipe-in transfer buffers

From: Catalin Marinas <catalin.marinas@arm.com>

When the HDC driver writes the data to the transfer buffers it pollutes
the D-cache (unlike DMA drivers where the device writes the data). If
the corresponding pages get mapped into user space, there are no
additional cache flushing operations performed and this causes random
user space faults on architectures with separate I and D caches
(Harvard) or those with aliasing D-cache.

(.................)

The PIO-MMC drivers walk through a scatter list via sg_miter_start() and
friends. Those helpers take care of this automaticly.
(Actually I just ran into a issue seems related to it. PIO SDHC

(.................)

My issues is with both I-D coherency and D-cache aliasing caused by
pages mapped in both user and kernel space (with different colours). The
flush_dcache_page() call should target both cases.

(.................)

We could of course flush the caches every time we get a page fault but
that's far from optimal, especially since DMA-capable drivers to do not
pollute the D-cache and don't need this extra flushing. Note that the
recent ARM processors have PIPT caches but separate for I and D and it's
the PIO drivers that pollute the D-cache.

The kernel API provides flush_dcache_page() to be called every time the
kernel writes to a page cache page. This is further optimised for
working in pair with update_mmu_cache() to delay the flushing until the
actual page is mapped into user space and this latter function is called
(which in general is not a cache maintenance function).

The problem with some PIO drivers and a filesystems like ext2 is that
there is no call to flush_dcache_page() when getting data into a page
cache page. Since the page isn't marked as dirty (PG_arch_1), a
subsequent call to update_mmu_cache() as a result of a page fault
doesn't flush the caches.

(.................)
(2nd issue, unnecessory DMA cache operation for PIO cause corruption, only on ARMv7 with speculative prefetch)

> This seems wrong to me. Buffers for control transfers may be transfered
> by DMA, so the caches must be flushed on architectures whose caches
> are not coherent with respect to DMA.
Indeed and that's what I mentioned in the comment. But we shouldn't have dma
cache maintenance operations done for the buffers which would use pio based transfer.
> Would you care to elaborate on the exact nature of the bug you are fixing?
On the OMAP4 (ARM cortex-a9) platform, the enumeration fails because control
transfer buffers are corrupted. On our platform, we use PIO mode for control
transfers and DMA for bulk transfers.

The current stack performs dma cache maintenance even for the PIO transfers
which leads to the corruption issue. The control buffers are handled by CPU
and they already coherent from CPU point of view.

(.................)


On map, buffers are cleaned if they're being used for DMA_TO_DEVICE and
DMA_BIDIRECTIONAL, or invalidated in the case of DMA_FROM_DEVICE.

However, because ARM CPUs can now speculatively prefetch, just leaving it
at that results in corruption of buffers used for DMA. So we have to
invalidate DMA_FROM_DEVICE and DMA_BIDIRECTIONAL buffers on unmap to
ensure coherency with DMA operations.

If the CPU writes to a DMA_FROM_DEVICE buffer between map and unmap, the
writes can sit in the cache, and on unmap, they will be discarded.

Cleaning the cache on unmap is not an option; that too can lead to DMA
buffer corruption in the DMA case.

USB and associated host driver must abide by the DMA API buffer
ownership rules otherwise the result will be data corruption; either
that or USB/host driver people need to have a discussion with the
DMA API authors to remove this sensible "restriction".






[PATCH] isp1760: Flush the D-cache for the pipe-in transfer buffers
http://lkml.org/lkml/2010/2/2/142


[RFC PATCH 0/4] PIO drivers and cache coherency
http://www.spinics.net/lists/linux-arch/msg09295.html

[RFC PATCH 1/4] pio-mapping: Add generic support for PIO mapping API
http://www.spinics.net/lists/linux-arch/msg09296.html

[RFC PATCH 2/4] pio-mapping: Add ARM support for the PIO mapping API
http://www.spinics.net/lists/linux-arch/msg09297.html

[RFC PATCH 3/4] pio-mapping: Use the PIO mapping API in libata-sff.c
http://www.spinics.net/lists/linux-arch/msg09298.html

[RFC PATCH 4/4] pio-mapping: Use the PIO mapping API in the ISP1760 HCD driver
http://www.spinics.net/lists/linux-arch/msg09299.html


swiotlb

Kernel development
The current 2.6 kernel is 2.6.7;...
http://lwn.net/Articles/89961/

DMA issues, part 2
[Posted June 30, 2004 by corbet]
http://lwn.net/Articles/91870/


PG_arch_1
http://www.takatan.net/lxr/source/include/asm-arm/cacheflush.h#L97

Linux ARM memory layout

./Documentation/arm/memory.txt

./arch/arm/mm/init.c

high_memory = __va((max_low << PAGE_SHIFT) - 1) + 1;
arch/arm/include/asm/pgtable.h
#define VMALLOC_OFFSET (8*1024*1024)
arch/arm/include/asm/pgtable.h
#define VMALLOC_START (((unsigned long)high_memory + VMALLOC_OFFSET) & ~(VMALLOC_OFFSET-1))

arch/arm/mach-ARCH/include/mach/vmalloc.h (platform dependent)
#define VMALLOC_END (PAGE_OFFSET + 0x20000000)

arch/arm/include/asm/memory.h
#define PAGE_OFFSET UL(CONFIG_PAGE_OFFSET)

.config
CONFIG_PAGE_OFFSET=0xC0000000

VMALLOC_START = high_memory + VMALLOC_OFFSET = CONFIG_PAGE_OFFSET+ram_size + VMALLOC_OFFSET
VMALLOC_END = CONFIG_PAGE_OFFSET + 0x20000000

==> available VMALLOC size = 0x20000000 - VMALLOC_OFFSET - ram_size = 512M -8M -ram_size

2010年2月7日 星期日

2010年2月5日 星期五

Performance tuning

  • Hardware optimization
    • CPU Speed
    • RAM speed
    • Bus (AXI/AHB) burst access
    • Ensure cache (L1/L2) is running in shortest delay/in fastest mode
  • Software optimization
    • compilier optimization (-O -O3)
    • Algorithm improving
    • Have all the buffers use cache, unless it is faster to use NCNB buffer, but that is usually not the case.

ARM11 MPCore 600MHz, DDR2 400MHz, with L1 and L2 cache enabled. 32-byte cacheline
time measured with spectrum by toggling GPIO, NCNB buffer allocated by dma_alloc_coherent, cacheable buffer allocated by kmalloc.

no op, just toggling GPIO: on 97ns, off 97ns
32-bit write-then-read (ncnb/cacheable+flush): 493/190+335.1 ns =>(-97) 396/93+238 ns
8 x 32-bit write-then-read (ncnb/cacheable+flush): 2082/754+372 ns =>(-97) 1985/657+275 ns

a cache flush is supposed equivalent to 8 32-bit memory write(32-byte cacheline) , but it seems that somehow it's not. And so do the 8 ncnb access are not 8 times of 1 ncnb access.

Though the result might not be so accurate, but if the driver would access a cacheline more than twice, then it is worth to use cacheable buffer. In some extreme case one might like to try it out, but cacheable buffer might still be the one

Linux ARM FIQ support

CONFIG_FIQ

arch/arm/kernel/fiq.c
http://lxr.linux.no/#linux+v2.6.32/arch/arm/kernel/fiq.c

Re: FIQ support on ARM-Linux
http://www.mail-archive.com/linux-arm@vger.rutgers.edu/msg04103.html

But the kernel doesn't give you a lot of help
to use FIQs; you have to do most of the work yourself. See arch/arm/kernel/
fiq.c for some example stuff, though it may not suit your needs. Really, it
all depends what you want to do.


笔记:linux中实现fiq模式(关于arm中断,唤醒中断)
http://blog.chinaunix.net/u3/99423/showart_2037446.html

AT91RM9200 FIQ FAQ and simple Example code / patch
http://warmcat.com/_wp/2007/09/17/at91rm9200-fiq-faq-and-simple-example-code-patch/
http://svn.openmoko.org/branches/src/target/kernel/2.6.24.x/patches/introduce-fiq-basis.patch

ARM中斷流程
http://stenlyho.blogspot.com/2008/08/arm.html

2010年2月4日 星期四

NoName XPE

[推薦新手優先觀看]NoName XPE 原理介紹及分析說明
http://nonamexpe.duc.cc/viewtopic.php?f=48&t=570

(080317更新)NoName Information Team XPE
http://www.gamemad.com/go/ShowPost.asp?ThreadID=14287