.text 0x00000000 0x3e0 cpu/arm11mpcore/start.o
.text 0x00011b80 0x400 board/cavium/cns3000/libcns3000.a(lowlevel_init.o)
if secondary_cores is put at:
0x 00,04,08,0c,10,14 is ok
0x 18,1c failed
add a ".align 5" to align secondary_cores
It is found that the alignment of following code marked in red in lowlevel_init caused the boot failed:
ldr r5, =0x35678855This movne is the very point that the secondary core jump from u-boot to Linux kernel.
cmp r6, r5
movne pc, r6
under failed situation, with RVDS on Core1 with no_reset_and_no_stop,
but I got an FFF00010 (DataAbort) @ 0x1077c, and the code seems changed, for previous WFI and movne section cannot be found at the same address.
kernel_start -> rest_init -> kernel_init -> smp_prepare_cpu_secondary -> poke_milo ->
ARM Linux Boot Sequence
The secondary boot failure is caused by kernel which decompress image to 0x8000(32kB), while the u-boot takes around 132kB from 0x0, and the function secondary_cores are linked below 32kB, therefore overwritten by decompressed kernel.
Although it is overwritten, the ICache is enabled on secondary core, therefore, in some situation SMP/SOP boot would pass if the required code are cached.
.align abs-expr, abs-expr, abs-expr
Pad the location counter (in the current subsection) to a particular storage boundary. The first expression (which must be absolute) is the alignment required, as described below.
Booting ARM Linux SMP on MPCore
Booting Linux SMP on MPCore
ARM Linux Booting Process (ARM920T)
arm smp support patch
Performance Measurement on ARM