little endian ARM CPU (LE CPU)
AXI, bus data bit 0~63
a big endian device w/ DMA master (BE CPU)
Says a LE CPU write a 64-bit value to an address in memory, later a BE CPU get the 64-bit value from the address. Will they get the same value?
One of my colleague said YES, because
BE CPU will get byte 0 from bus bit 56~63This access difference result in a 64-bit data swap, which cause the data of both CPU see the same value.
LE CPU will get byte 0 from bus bit 0-7
This is at least a fact on our SoC.
But, is this the default behavior or convention, which BE CPU/DMA master will get byte 0 from bit 56-63? (I don't know now)
It depends on the implementation. In this case we did a swap, the "Word Consistent Approach".
Endianness and ARM System Endianness
[wiki] Bit numbering
LSB 0 bit numbering
When the bit numbering starts at zero for the least significant bit the numbering scheme is called "LSB 0". This bit numbering method has the advantage that for any unsigned integral data type the value of the number can be calculated by using exponentiation with the bit number and a base of 2.
MSB 0 bit numbering
Similarly, when the bit numbering starts at zero for the most significant bit the numbering scheme is called "MSB 0".
Byte and Bit Order Dissection
Endianness of Bus
The bus we refer to here is the external bus we showed in the figure above. We use PCI as an example below. The bus, as we know, is an intermediary component that interconnects CPUs, devices and various other components on the system. The endianness of bus is a standard for byte/bit order that bus protocol defines and with which other components comply.
Take an example of the PCI bus known as little endian. It implies the following: among the 32 address/data bus line AD [31:0], it expects a 32-bit device and connects its most significant data line to AD31 and least significant data line to AD0. A big endian bus protocol would be the opposite.
For a partial word device connected to bus, for example, an 8-bit device, little endian bus-like PCI specifies that the eight data lines of the device be connected to AD[7:0]. For a big endian bus protocol, it would be connected to AD[24:31].
In addition, for PCI bus the protocol requires each PCI device to implement a configuration space. This is a set of configuration registers that have the same byte order as the bus.
Just as all the devices need to follow bus's rules regarding byte/bit endianness, so does the CPU. If a CPU operates in an endianness different from the bus, the bus controller/bridge usually is the place where the conversion is performed.
An alert reader nows ask this question, "so what happens if the endianness of the device is different from the endianness of the bus?" In this case, we need to do some extra work for communication to occur, which is covered in the next section.
Endianness of Devices
Kevin's Theory #1: When a multi-byte data unit travels across the boundary of two reverse endian systems, the conversion is made such that memory contiguousness to the unit is preserved.
We assume CPU and bus share the same endianness in the following discussion. If the endianness of a device is the same as that of CPU/bus, then no conversion is needed.
In the case of different endianness between the device and the CPU/bus, we offer two solutions here from a hardware wiring point of view. We assume CPU/bus is little endian and the device is big endian in the following discussion.
Word Consistent Approach
In this approach, we swap the entire 32-bit word of the device data line. We represent the data line of device as D[0:31], where D(0) stores the most significant bit, and bus line as AD[31:0]. This approach suggests wiring D(i) to AD(31-i), where i = 0, ..., 31. Word Consistent means the semantic of the whole word is preserved.
Byte Consistent Approach
In this approach, we do not swap bytes, but we do swap the bits within each byte lane (bit at device bit-offset i goes to bus bit-offset (7-i), where i=0...7) in hardware wiring. Byte Consistent means the semantic of the byte is preserved.
Endianness of Network Protocols
Bit Transmission/Reception Order
The bit transmission/reception order specifies how the bits within a byte are transmitted/received on the wire. For Ethernet, the order is from the least significant bit (lower wire address offset) to the most significant bit (higher wire address offset). This apparently is little endian. The byte order remains the same as big endian, as described in early section.