FPGA related

[wiki] FPGA
http://en.wikipedia.org/wiki/Fpga

Typical logic block

OpenCores
http://www.opencores.org/

Array(Row x Col) - memory provided (in bits)
Logic cell(aka. logic block)
slices - unknown, depends on FPGA manufacturer


Logic block include a LUT and a flip-flop

gate count(in equivalent NAND2 count)

gate count could be convert to logic cell used by a ratio of 8~1x, depend on the situation
e.g. 500k gate count will use about 50k FPGA logic cell

SafeXet EIP9X used 500k gate count
CavXXX VPX used 290k gate count

AES (Rijndael) IP Core: Overview
http://www.opencores.org/projects.cgi/web/aes_core/overview

Sample Synthesis Results for the Cipher Block

Technology	Size/Area	Speed/Performance
Xilinx Spartan IIe XS2V200-6	3497 LUTs (74 %), 1026 Regs. (21 %)	101 Mhz (1.08 Gbits/sec)
UMC 0.18u Std. Cell	38K Gates	265 Mhz (2.82 Gbits/sec)

Sample Synthesis Results for the Inverse Cipher Block

Technology	Size/Area	Speed/Performance
Xilinx Spartan IIe XS2V200-6	3393 LUTs (72 %), 883 Regs. (18 %)	85 Mhz (906 Mbits/sec)
UMC 0.18u Std. Cell	50K Gates	235 Mhz (2.5 Gbits/sec)

Sample Synthesis Results for the Cipher Block
the ratio of gates/LUTs (38k/3497) is about 10.8

Sample Synthesis Results for the Inverse Cipher Block
the ratio of gates/LUTs (50k/3393) is about 14.7

SPI core: Overview
http://www.opencores.org/projects.cgi/web/simple_spi/overview

130LUTs in a Spartan-II, 230 LCELLs in an ACEX

Serial Uart: Overview
http://www.opencores.org/projects.cgi/web/miniuart2/overview

Synthesis results
Xilinx:
• Spartan: XCS10-TQ144-4: 71 flip-flop
• Spartan-II: XC2S15-CS144-6: 153BELs@107MHz