http://en.wikipedia.org/wiki/Computer_memory
Computer memory types
- Volatile
- DRAM, e.g. DDR SDRAM
- SRAM
- Upcoming
- Z-RAM
- TTRAM
- Historical
- Williams tube
- Delay line memory
- Non-volatile
- ROM
- PROM
- EAROM
- EPROM
- EEPROM
- Flash memory
- NOR
- NAND
- Upcoming
- FeRAM
- MRAM
- CBRAM
- PRAM
- SONOS
- RRAM
- Racetrack memory
- NRAM
- Historical
- Drum memory
- Magnetic core memory
- Plated wire memory
- Bubble memory
- Twistor memory
- ROM
Static RAM(SRAM)http://en.wikipedia.org/wiki/Static_random_access_memory
does not need to be periodically refreshed, unlike DRAM, volatile
http://en.wikipedia.org/wiki/Flash_memory
single-level cell (SLC) devices
each cell stores only one bit of information.
multi-level cell (MLC) devices
can store more than one bit per cell by choosing between multiple levels of electrical charge to apply to the floating gates of its cells
- NOR
- Read
- provides an external address bus for read and program operations (and thus supports random-access);
- similar to reading from random-access memory, provided the address and data bus are mapped correctly.
most microprocessors can use NOR flash memory as execute in place (XIP) memory, meaning that programs stored in NOR flash can be executed directly without the need to first copy the program into RAM.
- Write
- unlocking and erasing NOR memory must proceed on a block-by-block basis.
- Erasure must happen a block at a time
- slow write speeds compared with NAND flash.
- Read
- NAND
These memories are accessed much like block devices such as hard disks or memory cards. Each block consists of a number of pages.- Read
- reading and programming is performed on a page basis
- reading and programming is performed on a page basis
- Write
- unlocking and erasing must be performed on a block basis
- Read
SLC Floating Gate NOR (100k~1000k) > MLC Floating Gate NOR, NAND Flash (100k)
http://www.toshiba.com/taec/Catalog/components/Description/images/NANDvsNOR.swf
Erase
SLC/MLC NAND (2ms) >> MLC NOR(900ms)
Program
SLC NAND(8MBps) > MLC NAND(2.4MBps) > MLC NOR(0.47MBps)
Read
MLC NOR(103MBps) > SLC NAND(24MBps) > MLC NAND(18.6MBps)
Density
NAND (128Mb~32Gb) > NOR(8Mb~512Mb)
http://www2.electronicproducts.com/NOR_and_NAND_flash_for_high-capacity_mobile_apps-article-m-systems-feb2006-html.aspx
NOR vs. NAND
| Characteristic | NOR | NAND |
| Density | 1 to 64 Mbytes | 16 Mbytes to 1 Gbyte |
| Code execution | Yes | No |
| Performance | Very slow erase Slow write Fast read | Fast erase Fast write Fast read |
| Reliability | High | Low |
| Ease of use | Easy | Complicated |
| Price | High | Low |
http://scottshulinux.blogspot.com/2008/10/nor-flash.html
http://scottshulinux.blogspot.com/2008/10/nand-flash.html
NAND flash benefits multimedia handsets
http://www.eetindia.co.in/ART_8800542316_1800009_NT_3b7bfbe6.HTM
在手機設計中採用NAND快閃記憶體
http://www.eettaiwan.com/ART_8800542727_628626_TA_6a05b30d.HTM
Multichip packages (MCP)
Package-on-package (PoP)
PoP technology is essentially an MCP stacked on top of a processor to save board space. This requires that the top memory PoP be compatible with the bottom processor. The memory alternatives described for MCP also apply to PoP. However, because of potentially tighter height restrictions, the maximum memory density that can be supported within PoP is typically less than that of MCP.
low-density RAM + NOR
pseudostatic SRAM (PSRAM) + NOR + NAND
DRAM + NAND
NAND flash and DRAM have to their advantage economies of scale as the two most widely used memory technologies.
controller is then incorporated with the MLC NAND device to manage error-code correction (ECC), wear leveling and bad block management requirements of the MLC NAND die, relieving the host processor of this task.
single-level cell (SLC) NAND
multilevel cell (MLC) NAND
SLC NAND interface
MMC interface
SD interface
Toshiba's mobileLBA NAND
use a NAND die + controller, where the NAND die can be partitioned between SLC NAND and MLC NAND
沒有留言:
張貼留言